module ex3_fbctl(
  input         i_ls,
  input         i_valid,
  input         i_ls_b,
  input         i_ls_h,
  input  [29:0] i_ls_word_addr,
  input  [ 1:0] i_ls_byte_addr,
  input         i_ls_second_cycle,
  output        o_fb,
  output        o_valid,
  output        o_ls_second_cycle,
  output [29:0] o_ls_word_addr
);

wire addr_unaligned;
wire done;

assign addr_unaligned =
  i_ls_h ? i_ls_byte_addr == 2'b11 : i_ls_b ? 1'b0 : |i_ls_byte_addr;
assign done = ~i_ls | (~addr_unaligned | i_ls_second_cycle);
assign o_fb = ~done;
assign o_valid = i_valid & done;
assign o_ls_second_cycle = 1'b1;
assign o_ls_word_addr = i_ls_word_addr + 30'b1;

endmodule
